Flip chip technology is the fastest growing chip interconnect technology as it allows very large numbers of I/Os. Thus, the footprint of chips with low numbers of I/O's can be made very small. This is also true for associated packages such as chip-scale packages.
FIGS. 1A-1C show a prior art device 10 comprising a fragment of a semiconductor chip 11 on which C4 solder balls 12 are supported on pads 13 on the chip 11 (which may be composed of silicon). There is underfill 14 formed on the surface of the chip 11 and between the C4 solder balls 12. In FIG. 1A, the underfill 14 does not cover the C4 solder balls 12 but leaves the top surfaces thereof exposed. In FIG. 1B, the underfill completely covers the C4 solder balls 12 leaving the top surfaces thereof unexposed. In FIG. 1C, the underfill 14 does not cover the C4 solder balls 12 and leaves the top surfaces and portions of the upper surfaces thereof exposed.
FIGS. 2A-2C show a prior art device 10 comprising a fragment of a semiconductor chip 11 on which cylindrical bumps 16 with flat tops are supported on pads 13 on the chip 11. There is underfill 14 formed on the surface of the chip 11 and between the cylindrical bumps 16. In FIG. 2A, the underfill 14 does not cover the cylindrical bumps 16 but leaves the top surfaces thereof exposed. In FIG. 2B, the underfill completely covers the cylindrical bumps 16 leaving the top surfaces thereof unexposed. In FIG. 2C, the underfill 14 leave upper portions of the cylindrical bumps 16 exposed and leaves the top surfaces and portions of the sidewall surfaces thereof exposed.
The major advantage of flip chip technology is that it can utilize the total chip area to make the I/O connections, while wire bonding uses only the chip periphery. Referring to FIGS. 1A-1C and 2A-2C, a disadvantage of flip chip technology is that stresses that arise from the thermal mismatch between the chip 11 Coefficient of Thermal Expansion (CTE) and the CTE of the substrate are borne fully by the solder bumps (solder ball bumps 12 and cylindrical bumps 16), e.g. Controlled Collapse Chip Connections (C4s), used to make the interconnect between a chip and substrate 11. In order to ameliorate the stresses in flip chip packages the region between the chip and the substrate is filled with an underfill material which encapsulates the solder bumps or C4 connections. The underfill material may be an Over-Bump Applied Resin (OBAR). The over bump applied resin underfill material is placed between the chip and the substrate and acts as encapsulant of the solder bumps and as an adhesive between chip and substrate. The effect of such underfills is that the long-time reliability of underfilled flip chip packages is greatly enhanced compared to non-underfilled counterparts.
Such resin underfill material 14 can be applied by capillary flow, using a so-called no-flow process or by wafer-level applied processes. There are several wafer-level applied underfill processes, among them a Wafer-Level Underfill (WLUF) process which uses an over bump applied resin, that is then b-staged, followed by dicing the wafer to singulate chips and finally joining the chips with the WLUF layer to substrates. U.S. Pat. No. 6,919,420 Buchwalter et al which is incorporated herein by reference describes the WLUF process employed in connection with this invention.
U.S. Pat. No. 6,924,171 of Buchwalter et al., which is incorporated herein by reference, illustrates a method of flip chip joining of chips to substrates in accordance with the method of this invention.
There is the problem that an over bump applied resin layer can obscure the pattern of the electrical connect structure (C4s, copper studs, micro-bumps and similar structures) and other alignment marks making it difficult to align a wafer for dicing, a wafer for wafer to wafer joining, or a singulated chip for joining to its respective substrate or to another chip in 3-D applications. A singulated chip is a single chip produced by dicing.
To align wafer or chip, the over bump applied resin is a material which must be either transparent or translucent and the thickness of the layer must be thin enough so that the pattern is still visible. While it may be advantageous to use a thicker over bump applied resin coating, the thicker the underfill layer, the less visible are the connect structures or other alignment marks. Thus, alignment of wafer or chip under such conditions is a significant problem.
FIGS. 3A-7A show a set of prior art plan views of exemplary prior art features on fragments of chips 11 with different patterns which are to be identified and for which the alignment needs to be determined. FIGS. 3B-7B show cross-sectional views of the features shown in FIGS. 3A-7A.
FIGS. 3A and 3B show a fragment of a chip 11 supporting a conductive metallic pad 13 on which a bump 20 has been formed. The bump 20 has an elliptical shape in both the plan and the cross-sectional views.
FIGS. 4A and 4B show a fragment of a chip 11 supporting an alignment mark 22 which has an cross shape in the plan view and a rectangular shape in the cross-sectional view.
FIGS. 5A and 5B show a fragment of a chip 11 supporting a conductive metallic pad 13 on which a bump 24 has been formed. The bump 24 has a circular pattern in the plan view and a semi-spherical shape in the cross-sectional view.
FIGS. 6A and 6B show a mark 26 which has a hollow, annular shape in plan view and in the cross-sectional view.
FIGS. 7A and 7B show a fragment of a chip 11 supporting a conductive metallic pad 13 on which a bump 28 has been formed. The bump 28 is solid and has a round shape in plan view and a rectangular shape in the cross-sectional view.
While it is often possible to align wafers and chips in which the connect structures are visible to the naked or aided eye by manual alignment, this process is undesirable in a manufacturing environment in which parts must be aligned quickly with high accuracy by an automated process.
Accordingly, a need exists for a process to recognize the exact or approximate location of one or more of the connect structures or other alignment marks which are at least partially obscured by an over-bump applied material such as used in the WLUF process. These and other needs are met by the recognition method of the invention described in the following. Other advantages of the present invention will become apparent from the following description and appended claims.
Heretofore, in the case of the surface of an over bump applied resin or over bump applied material in an application with features such as coated C4 balls the optical system has not been able to automatically recognize the diffuse location of the partially obscured features (C4 balls) and has been unable to identify the location thereof exactly or approximately.